Lots of thinking to be done about the 8-bit computer architecture. Particularly the 8-bit arithmetic and logic unit (ALU). Additional thoughts on literals (immediates/constants) and conditional branching.
By Julian
Youtuber, shed dweller, solar charge controller aficionado
Julian…if you use Subtract and branch if result is less than or equal to zero also known as SUBLEQ….then a one instruction computer is Turing complete. There is even an OS for such a computer. It is very interesting working out how to do various things with just SUBLEQ.
Brilliant – Thank you! Why not use a couple of 245N bi-directional octal trans to define your functions (literals)? A couple of these will give you 4 functions. Just tie the input pins high or low according to your output function. Because these are bidirectional with a direction being defined on pin 1 – you can lay two transceivers down almost aligned with each other. Have the top 4 bits to go to a common 1C0 to 1C3 '253 bus' and the bottom 4 bits go to a common bus for 2C0 to 2C3. Use a 138N or similar to select which transceiver (function) to use and an inverter on the HC253 G lines to select the 'top' or 'bottom' function. I noticed the HC253 has a tristate output. Could anyone advise me if 74LS153Ns will be OK? These give a LOW output if not selected.
Instead of stacking multiplexers, I'd just burn an eprom, with all of the address inputs being the function you want plus the data of at least one of the operands, then you get what you want by simply reading it…
Oh, and if you're moving away from TTL and going completely to CMOS, then it's not Vcc, it's Vdd! 🙂
Julian, the 74HC253 is configured such that the SELECT inputs (A and B) are shared by both 4-1 mux channels. Does this not mean you'd need 8 chips total since you can only make use of one chip per bit?
Edit: Ah actually you're planning two logic units with the same A and B inputs, so you can use one half of each chip per LU for 8 chips total, 4 per LU.
Name of that led
Do those LED strips have internal current limiting resistors?
Please provide me with the schematic. I need it
starts thinking about using the 8 line de/mux chips as three input logic gates
Wow I am surprised that no one has asked if it can "run crisis" the viewers must be smarter hear.
where do you get those wires? what are they called?
Would it make this computer more complicated if you would read both data from same memory? If you make state counter and, depending on how you arrange your data, use most or least significant bit to control when u read memory addres or opcode / data. Maybe it could even be four state counter and you would have opcode, data location, data and next instruction in 32 bit. For me this seems like it would fit for copy-only type computer.
Does this make any sense?
you dont need jmp to be turin-complete. The mov instruction is turin-complete by itself.
just getting into Raspberry and ardunio and came across this. can't wait till its finished. hope you are going to make a full list of parts needed to build it myself. please hurry with the next instalment.
Interesting idea for an ALU, however, I think it may be overly complicated. If you are willing to get rid of a few operations (which can be done in multiple steps), you can reduce your design to being an A/0 mux on the A input on the ALU, and your 4/1 mux on the B input as you had designed. You can even replace the A/0 mux with a simple 8-bit and gate, where if you pass 1 as the input, you get A, otherwise you get 0, since every operation you listed (including in your following video) can be done in either a single configurable truth-table, and an A/0 mux.
As an aside, this is exactly how FPGAs and CPLDs work, being mostly composed of muxes (usually 4 to 1 and 2 to 1), and the truth-tables are populated when the device is programmed and stored in SRAM.
With that said, even though you wanted to avoid programming parts of the design, it might make sense to use a CPLD for your ALU (there are some breadboard breakout designs – I found some for the coolrunner with a quick search). It would allow you to consolidate the adder, and the muxes into a single part. If you decide to use a CPLD, and want some help programming it / writing the HDL, let me know.
A final comment about your ALU, you might want to also add an output zero test, could be useful for testing if A > B, etc. You can do that with a big 8-input NOR gate.
Sorry Julian, but are you saying 'literal', 'littoral', 'litrel' or something else? And what are they, please? That's where you lost me. Thanks.
Fascinating mate.